A 79.2W 19.5kHz-BW 94.8dB-SNDR Fully Dynamic DT Σ ADC using CLS-Assisted FIA with Sampling Noise Cancellation
نویسندگان
چکیده
This brief proposes a fully dynamic discrete-time (DT) Σ ADC using correlated level shifting (CLS)-assisted floating inverter amplifier (FIA) with sampling noise cancellation (SNC) technique. The CLS-assisted FIA improves gain single-stage configuration, which has lower input-referred than the cascaded one. In combination proposed SNC, contribution of 1st-stage integrator can be minimized. We also propose novel passive adder that avoids unwanted inter-stage loading without speed penalty. prototype fabricated in 65 nm bulk CMOS process realizes operation and achieves 94.8 dB SNDR an OSR 256 for 19.5 kHz bandwidth while consuming 79.2 W from 1.2V supply at 10 MHz frequency. Schreier Walden FoMs are respectively 178.7 45.2 fJ/conv.-step, best among recent DT ADCs similar bandwidth.
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ژورنال
عنوان ژورنال: IEEE Transactions on Circuits and Systems Ii-express Briefs
سال: 2023
ISSN: ['1549-7747', '1558-3791']
DOI: https://doi.org/10.1109/tcsii.2023.3255866